BRAD SIDRICK EXPERIENCE (CONTINUED) PAGE 3 LEGACY ENGINEERING LLC

GERALD J. ADAMS

BRAD SIDRICK

EXPERIENCE (CONTINUED) Page 3

Legacy Engineering, LLC

18662 MacArthur Blvd. Suite 457

Irvine, CA 92612-1426

Telephone: (949) 794-5860

Home Page: www.Legacyeng.com

BRAD SIDRICK

OBJECTIVE

I am interested in assignments where I can use my experience with Spice, VHDL, Verilog, FPGA’s, OrCAD in the analysis, design and testing of analog and digital circuits for medical devices, flight controls, motor controllers and data acquisition systems.

EXPERIENCE

02/2012 to 08/2012: Adsys Controls, Irvine, CA

VHDL design, simulation and test of a control module for a high speed analog I/O board with a LabVIEW interface which had a Virtex 5 FPGA, 5 MHz DAC and 40 MHz ADC. Reviewed the design and found signal integrity, feedback, bias, schematic and layout problems. LTspice simulation of clock terminations, filter distortion, DAC settling time and switching regulators.

11/2011 to 01/2012: Ecliptic, Pasadena, CA

Reviewed Verilog and VHDL code for a camera’s command and telemetry interfaces with a Virtex 5 FPGA. Wrote Verilog and VHDL testbenches and FIFO test code for a CCSDS framer and packet data using Xilinx ISE and ISim.

08/2010 to 01/2011: Fresenius, Lake Forest, CA

Designed and tested circuitry for a temperature compensated fluid conductivity sensor and camera with an Actel A3P250 FPGA, USB and Ethernet Interfaces for a kidney dialysis machine. PSpice simulation of an active filter, synchronous detector and thermistor linearizing. Schematic capture using OrCAD.

11/2008 to 03/2010: Parker Hannifin, Irvine, CA

DO-254 flight control design and testing of SHARC 21369 DSP and TMS320F2812 DSP and Actel A3P1500 FPGA based command and monitor lanes for a Bombardier CSeries Generic Fly By Wire Remote Electronic Unit which contains ARINC 429 interfaces, LVDT, solenoid, and pressure sensor signal conditioning. PSpice simulation of LVDT signal conditioning and sampling. Generated TTP timing using VHDL. Schematic capture using Mentor DxDesigner.

03/2004 to 04/2007: Honeywell, Torrance, CA

CPLD design using VHDL for the Xilinx XC95144XL which controlled solenoids in the CX/PX Ram Air Turbine Emergency Deployment Unit. Designed and tested TMS320F2812 DSP based PM and induction motor controllers which included a 28V inverter for the Global Hawk Antenna Drive and 270V inverters for A380 and OBIGGS. PSpice simulation of a 12KW ATRU for CE101, 20 Khz SVM inverter, brake driver, floating gate drive supply and temperature sensors. Designed and simulated a soft start and power sequencer for a JSTARS dc/dc converter. Simulated the stability and current limiting of the power supply, dc/dc converter and linear regulator. Schematic capture using OrCAD.

09/2002 to 11/2002: Irvine Sensors, Costa Mesa, CA

Designed a PCI Mezzanine Card which had 2 66 Mhz 64 bit PCI cores in Xilinx Virtex II FPGA’s and 200 Mhz DDR SRAM that interfaced with a 3 Dimensional Analog Neural Network. Simulated and tested a one wire temp sensor and modified the VHDL code. Schematic capture using OrCAD.

03/2000 to 03/2002: DRS Sensors, Torrance, CA

Analog and digital design and testing of FLIR controls for the M1 Tank and Bradley Fighting Vehicle which included RS-170 video, frame grabbers, C40/VME and C33/CAN interfaces. FPGA design using Verilog and VHDL for the Altera 20K200. PSpice simulation of a PLL, ADC, solid state relays and pulse transformers. Schematic capture using OrCAD and PADS.

08/1996 to 01/2000: PerkinElmer, Long Beach, CA

Re-designed and tested TI C50, 82 , AD 2181, 80C592, 89C55 based metal detectors and X-ray baggage scanners which are used in airports to identify weapons and explosives. This included PCI, SCSI, CAN interfaces, DC/DC converters, battery chargers, phase lock loop, H-Bridge with controller, and a 14 bit 1.2 MSPS ADC and image processor for a CT scanner. Noise analysis and simulation of photo diode amplifiers, photo multiplier tube signal conditioning, filters and pulse generators using PSpice and IsSpice. CPLD design using Verilog and VHDL for the Altera 7064 and the Lattice 1016. Schematic capture using OrCAD and Viewlogic.

12/1994 to 05/1996: Parker Hannifin, Irvine, CA

Designed and tested 80196 based controller and analog I/O boards for F-18,15 Stabilator ElectroHydrostatic Actuator motor drivers which contained MIL-STD-1773, 1553, ARINC 429 interfaces, LVDT, RTD, and pressure sensor signal conditioning. Worst case, failure analysis and redesigned the Embraer 145 Yaw/Roll trim actuator timer to meet RTCA/DO-160 EMI requirements. CPLD design using ABEL for the WSI PSD403 and AHDL for the Altera EPM5130. Schematic capture using Viewlogic and OrCAD.

12/1992 to 07/1994: Alcon Surgical, Irvine, CA

Failure analysis, redesigned and tested the Universal II and MVS Plus 8085 and 8032 based opthalmic instruments used in vitreoretinal surgery which were recertified to IEC 601. Changes included redundant ground fault detection, solenoid, stepper motor, and illuminator control logic, laser power monitoring, and watchdog timers for ultrasonic phacoemulsification, aspiration, and coagulation. ATV2500, 750, 26V12, and 16V8 PLD design using ABEL. Schematic capture and timing simulation using OrCAD.

09/1992 to 11/1992: Hughes-Avicom, Glendora, CA

Reviewed, redesigned, and tested a battery charger and DC/DC converters for the File Server and Primary Access Terminal power supplies in a Northwest 747 airline in flight entertainment system.

10/1988 to 07/1990: Teledyne Controls, Los Angeles, CA

Analog design for the FAA Runway Visual Range program which is an 8097 and 80186 based airport data acquisition system. System analysis, circuit design, test equipment design and testing which included BER, EMI, and lightning per MIL-STD-461 and RTCA/DO-160. Designed a BELL 202 modem for a 5 nm UTP cable, signal conditioning for the Visibility and Ambient Light Sensors, Runway Light Intensity Monitor, power monitoring, battery backup, and a time code IRIG demodulator. Optimized component values for a line simulator using PSpice.

01/1985 to 07/1986, 07/1987 to 01/1988: TRW, Redondo Beach, CA

07/1987 to 01/1988: Reviewed and conducted a worst case analysis of the Signal Processor Unit for the Visible and Ultraviolet light Experiment, which is an instrument for the DSP Satellite. Designed and tested the GSE which simulated the Attitude Control System and Telemetry Processor. Designed STE for a TMS32020 Signal Processor Board.
01/1985 to 07/1986: Designed, tested, performed the integration of HP-1000 and PC based ATE for MILSTAR. This included system timing, control and interrupt logic, analog I/O, and self test for the Input Output Expander, Crosslink and Message Processor. 82S105 and 22V10 PLD design using ABEL.

08/1984 to 12/1984: McDonnell Douglas Helicopters, Culver City, CA

Reviewed and redesigned the Magazine Controller, which is a servo loop for the Ammunition Handling System on the AH-64 Helicopter. Made design changes and EMI fixes to the Rounds Counter and Gun Control Box in the Area Weapon System.

01/1984 to 07/1984, 02/1983 to 05/1983: 4C, Torrance, CA

Designed and tested the Universal Tactical Link Modem - 2 and part of the trunk interface between the mux and crypto gear for a secure telecom unit. This included a frequency synthesizer, transmitter, receiver, and bit synchronizer. Filter analysis using PSpice.

10/1983 to 01/1984: Hughes Aircraft, El Segundo, CA

Conducted a worst case analysis and redesigned of analog circuits for the HS-393A Satellite Cradle Driver Interface Unit which provides the Shuttle launch controls. Wrote the test plan and supervised the breadboard checkout that included EMI testing per MIL-STD-461 and 1541. EMI filter transient analysis using SPICE.

07/1982 to 01/1983: TRW, Redondo Beach, CA

Analog and digital circuit design and worst case analysis of the DSP-1 Satellite 14 Electrical Distribution Unit Logic Slice which controls spacecraft deployment. This included solar panel actuation and power monitoring.

02/1982 to 06/1982: McDonnell Douglas Helicopters, Culver City, CA

System and circuit design for PDP 11/23 based AH-64 Helicopter trainers, which included an ARINC 429 encoder/decoder, a MIL-STD-1553 interface between an RT and a Heading Attitude Reference System , and a ASCII keyboard encoder. Wrote a software spec which defined the simulation requirements for the Digital Automatic Stabilization Equipment, a fly-by-wire backup flight control system.

09/1981 to 11/1981: Honeywell (Garret), Torrance, CA

System design of the 8086/7 based IEC-4 fuel control system for a turbo prop engine which involved CPU/memory architecture, analog I/O, and BITE. Wrote the hardware design spec.

11/1980 to 05/1981: TRW, Redondo Beach, CA

Designed HP-1000 based GSE for spacecraft instruments. Analyzed the HALOE instrument/GSE interface and designed the GSE power control subsystem for the instrument and blackbody. Preliminary system design of an 8085 based CAMAC simulator for the ion propulsion system SEPS.

06/1980 to 10/1980: Northrop Electronics, Hawthorne, CA

Designed a 102 MHZ frequency synthesizer, range counter and a 1553B buffer memory for a tactical data link in an airborne transceiver for a reconnaissance plane and a ground modem. Used MECL III and 10K with microstrips.

02/1980 to 06/1980: McDonnell Douglas Helicopters, Culver City, CA

System analysis and design changes for testability of the YAH-64 Helicopter flight control system. Wrote a software spec that defined LRU fault isolation requirements.

05/1979 to 02/1980: Hughes Aircraft, El Segundo, CA

System and circuit design of ATE for the F-18 Radar which included HP-1000 interfacing, 1553A bus control logic, and self test.

02/1979 to 04/1979: Magnavox, Torrance, CA

Made design changes and wrote the performance specs for 3 hybrid modules in the spread spectrum USC-28 Satellite Receiver involving TDMA timing, Data IPM, and baseband interfacing.

11/1978 to 02/1979: TRW, Redondo Beach, CA

Designed a manual board tester to checkout the XMT/RCV subassembly in a secure T1 WAN. Defined the test specs and wrote the test procedure.

05/1978 to 10/1978: Hughes Aircraft, El Segundo, CA

Product design and system integration of ATE for a satellite multiplexer which included power control and distribution, packaging, and troubleshooting.

06/1977 to 04/1978: National Semiconductor, San Diego, CA

Designed an optical scanner with 5 mil resolution controlled by a 6800 over the IEE-488 bus. Failure analysis on MECL 10K IC's.

09/1975 to 06/1977: Solar Turbines, San Diego, CA

Designed an 8080 based data acquisition and control system for gas turbines. Supervised a metrology lab and wrote calibration procedures for test equipment and engine controls.

02/1974 to 08/1975: General Dynamics, San Diego, CA

Worst case analysis of amplifiers and filters using SPICE. Designed a 1 MHZ AM/FM function generator.

06/1973 to 02/1974: NCR, San Diego, CA

Troubleshooting the NCR 605 mini computer and a 1.8 KBPS FSK modem in a datacom system. Liaison between engineering and manufacturing.

EDUCATION

BSEE – UC Berkeley, CA

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